1. Field of the Invention
The present invention relates to an apparatus and method for correcting an output signal of an FPGA (Field Programmable Gate Array)-based memory test device, and more particularly, to an apparatus and method for correcting an output signal of an FPGA-based memory test device, wherein output of address, data and clock through a pattern generator to test memory is implemented with a programmable logic such as FPGA and thereby accuracy of output timing of the signal for memory testing may be increased, ultimately enhancing performance (accuracy) of a memory tester.
2. Description of the Related Art
In conventional memory test devices, internal operation is carried out entirely based on a reference clock. As address or data for memory becomes faster, not only individual output timings and phases but also clocks between command signals become different.
Korean Patent No. 540506 (Algorithm pattern producer for testing memory device and memory tester using the same) discloses a technique for a data comparing part configured to compare test data with data produced from a data producing part with respect to individual clock cycles and to store information about fail memory.
Specifically, as illustrated in FIG. 1, in the technique for compensating for the output signal of the memory test device, a delay device 2 per output signal is additionally provided, and the output signal which is directly measured from the outside is applied to the delay device 2, or is fed back to a correcting device 3 to measure a difference between the signals. Then, the signal difference per output is compensated using the delay device 2, thus recompensing the output signal of the memory test device.
However, in the conventional memory test device, the correcting device 3 is separately provided to correct the output signal, and to measure the difference between the signals so as to be compensated again using the delay device 2, undesirably incurring economic and spatial loss.